A layout of a conventional amplification type solid state imaging device will be described below with reference to FIG. 10. As shown in FIG. 10, the amplification type solid state imaging device is configured by forming a light-receiving portion 112, a horizontal scanner 114, a vertical scanner 115 and a noise rejection circuit 120 on a semiconductor substrate 117 (see Patent Document 1, for example).
The light-receiving portion 112 is configured by arranging a plurality of pixels one-dimensionally or two-dimensionally. Each pixel has a photoelectric conversion portion 112a for converting incident light to a signal charge and an outputting portion (not shown) for outputting an electric signal corresponding to the amount of the signal charge. In the example as shown in FIG. 10, the pixels are arranged two-dimensionally.
A light-shielding layer 111 is provided on the upper part of the light-receiving portion 112. Opening windows 116 are formed in the light-shielding layer 111 so that light will enter the respective photoelectric conversion portions 112a. As a result, light enters only the photoelectric conversion portions 112a of the respective pixels, while entry of light into the remaining part of each pixel will be restricted. The opening windows 116 are formed by forming a film to cover the light-receiving portion 112 and by removing the film partially and selectively.
The light-shielding layer 111 is formed also by forming a film of an electroconductive material. Furthermore, a wiring 118 is connected to the light-shielding layer 111. The wiring 118 is applied with a voltage (Vsd) for providing a ground potential (GND) so as to stabilize the well of the light-receiving portion 112.
The horizontal scanner 114 and the vertical scanner 115 read out sequentially electric signals generated at the respective pixels of the light-receiving portion 112 in an X-Y addressing scheme. Specifically, the vertical scanner 115 performs selection and control in the row direction at the plural pixels. The pixel signals of the row selected by the vertical scanner 115 are outputted to the noise rejection circuit 120. The pixel signals outputted to the noise rejection circuit 120 are outputted for each pixel due to a drive of a horizontal selection transistor 129 (see FIG. 11) by the horizontal scanner 114.
As shown in FIG. 10, a wiring layer 113 is arranged between the noise rejection circuit 120 and the light-receiving portion 112. The wiring layer 113 is used for an output control when the pixel signals of the row selected by the vertical scanner 115 are outputted to the horizontal scanner 114. Specifically, the presence/absence of the outputting is decided on the basis of the level of the voltage (Vnc) applied from the wiring 119 to the wiring layer 113. This will be described more specifically with reference to FIG. 11 below.
The noise rejection circuit 120 is provided in a region between the light-receiving portion 112 and the horizontal scanner 114 on the semiconductor substrate 117, and it suppresses spurious signals for the pixel signals read out from the light-receiving portion 112. Specifically, the noise rejection circuit 120 suppresses and rejects noise caused by a dispersion of the amplifying transistors (not shown) that form the respective pixels.
Here, the configurations of the light-receiving portion 112 and the noise rejection circuit 120 as shown in FIG. 10 will be described specifically with reference to FIGS. 11A and 11B. FIGS. 11A and 11B are diagrams showing one example of a unit pixel and a noise rejection circuit. FIG. 11A is a circuit diagram of a unit pixel and a noise rejection circuit, and FIG. 11B is a timing chart of pulse signals applied to signal lines. The noise rejection circuit 120 is formed of a plurality of unit circuits arranged horizontally. FIG. 11A shows only one of the unit circuits forming the noise rejection circuit 120.
In FIG. 11A, 135, 136 and 123 denote a row reset line, a row selection line and a vertical signal line respectively. A reset signal RS is inputted to the row reset line 135. A signal TR is inputted to the row selection line 136. As shown in FIG. 11A, the unit pixel 131 includes a photodiode 132 and three transistors. Among the three transistors, 133 denotes a transfer transistor and 134 denotes an amplifying transistor.
The noise rejection circuit (unit circuit) 120 includes a clamping capacitor (CCL) 125, a sampling capacitor (CSP) 128, a vertical-signal-line noise-rejection-circuit connection transistor 124, and a clamping transistor 126. The vertical-signal-line noise-rejection-circuit connection transistor 124 is used for switching signal transmission from the vertical signal line 123 to the noise rejection circuit 120, and it has a gate electrode to which an input signal SP is inputted. The clamping transistor 126 has a gate electrode to which an input signal CL is inputted. In FIG. 11A, 129 denotes a horizontal selection transistor.
In FIG. 11B, 141 denotes a horizontal blanking period, and 142 denotes a horizontal signal outputting period. As shown in FIG. 11B, in the first half and the latter half of the horizontal blanking period 141, the noise rejection circuit 120 allows the clamping capacitor (LCL) 125 to clamp a pixel signal outputted from a pixel and a reset signal RS by using pulses of the input signal CL and the input signal SP, and allows the sampling capacitor (CSP) 128 to sample. As a result, since subtraction of the pixel signal and the reset signal RS is performed by the sampling capacitor (CSP) 128, noise will be suppressed and rejected.
FIG. 12 shows a cross section of the amplification type solid state imaging device as shown in FIG. 10. In FIG. 12, the same components as those in FIG. 10 or FIG. 11 are assigned with the same reference numbers. In FIG. 12, parts provided with the same hatching patterns indicate that the parts have substantially the same functions.
In FIG. 12, numerals 121, 122 and 127 denote an element isolation region, an active region and a contact plug respectively. Numerals 130a-130c denote polysilicon wirings laid out in a plane, 137 denotes an insulating layer, and 138 denotes a well. In FIG. 12, the semiconductor substrate 117 and the insulating layer 137 are indicated without hatching.
As shown in FIG. 12, in the noise rejection circuit 120, the wiring layer 113 is connected via the contact plug 127 to the active region 122 in the vicinity of the sampling capacitor 128. The voltage (Vnc) applied to the wiring layer 113 provides a GND potential to the sampling capacitor 128. Therefore, by changing the voltage (Vnc) applied to the wiring layer 113, switching can be carried out at the time of transferring signals from the respective pixels 131 to the horizontal scanner 114 through the noise rejection circuit 120.
Patent document 1: JP 2001-15725 A